Nonvolatile ferroelectric random access memory (FeRAM) devices represent an emerging, multibillion-dollar market. The most advanced FeRAMs utilize a 1-transistor/1 capacitor (1T1C) cell technology and a destructive read out (DRO) scheme. These devices compete with EEPROMs, battery backed static RAMs (BBSRAMs), and Flash nonvolatile memory devices.
FeRAM is a type of semiconductor memory, constructed similarly to a Dynamic Random Access Memory (DRAM), but which stores bits of data without the need for power (nonvolatile characteristic). FeRAMs have gained recent interest because of the possibility that they could become the ideal memory of the future, replacing standard mass-produced DRAM. Although the basic fundamentals of ferroelectricity were discovered in the 1920's, developments within the last fifteen years regarding the use of thin ferroelectric films may now make it practical to develop a dense memory with ideal nonvolatile memory performance characteristics. Ferroelectric materials exhibit ferroelectric behavior below a critical temperature, known as the Curie temperature. The Curie temperatures of many ferroelectric materials are above 200° C. allowing them to be used as storage elements for nonvolatile semiconductor memories.
Prior art FeRAMs operate using an array of memory cells, which contain capacitors, built of a special dielectric material (a ferroelectric) sandwiched between two conducting material (electrode) layers. The special ferroelectric material is comprised of a lattice of ions, in which one of the ions in each unit cell has two stable states on either side of the center of the unit cell along an elongated axis as shown in FIG. 1a. When a voltage is applied across the top and bottom electrodes of a ferroelectric capacitor, the movement of these charged center ions creates a charge displacement within the dielectric. This charge displacement can be sensed as a current flowing between the electrodes of the ferroelectric capacitor. The charge displacement within a ferroelectric capacitor is often displayed as a hysteresis curve, where the polarization of the ferroelectric layer is plotted against the applied electric field, as shown in FIG. 1b. 
FIG. 1c shows a schematic of a 1T1C memory cell. When a positive electric field is applied across a negatively polarized ferroelectric capacitor, the center ions of the unit cells switch to positively polarized states. This ion movement can be sensed as a current flow between the electrodes of the ferroelectric capacitor. When this electric field is removed, the polarization settles to the state labeled “+Q0” (See FIG. 1b). If a negative external electric field is then applied across the ferroelectric capacitor, the center ions of the unit cells switch to negatively polarized states. When this electric field is removed, the polarization settles to the state labeled “−Q0”. FeRAMs offer an advantage over DRAMs because ferroelectric polarization can be retained in either state, +Q0 or −Q0, for a very long time (retention) without continuously applied power (nonvolatility). Unlike other nonvolatile memory elements, ferroelectric capacitors can be switched from state to state many times (>1010 cycles) without wear-out (fatigue). Also, because the ferroelectric capacitors operate at low voltage, there is no need for high voltages provided by charge pumps to program (write) the memory as required for some nonvolatile memories (e.g., EEPROM and Flash). The low programming voltages ultimately allow ferroelectric memory cells to scale to smaller dimensions than Flash memory.
The prior art for processing FeRAMs requires the fabrication of ferroelectric capacitors after all of the underlying CMOS circuitry has been fabricated just prior to metalization. A typical cross section of a 1T1C cell has a ferroelectric capacitor placed on the field oxide, and is connected to the transistor with a local interconnect. This creates a processing concern, because ferroelectric materials must be activated after deposition at high temperatures. When the underlying CMOS circuitry is heated to high temperatures, hydrogen is released, which degrades the ferroelectric film. Depositing the metalization interconnect layers can also produce hydrogen. Thus, a hydrogen barrier must be added to protect the ferroelectric capacitors. Also, some ferroelectric materials are very sensitive to moisture, which can be formed when hydrogen is released. Finally, when dense memories are fabricated, planarization techniques are commonly used. Most processes require interconnect metalization to be added before the ferroelectric materials are deposited and activated. This interconnect metalization cannot withstand the high temperatures of ferroelectric film activation. All of these problems have slowed the development of dense FeRAMs and have clouded the future for an ideal memory.
The overriding disadvantage of prior art 1T1C cell memories is that under the best of circumstances they cannot be scaled aggressively enough to compete with Flash memory since they require 2 elements per cell compared to a single element in flash. With comparable design rules a prior art FeRAM has a cell size at lest twice the cell size of flash.
A cross section and a diagram of the proposed 1T-cell, the subject of this invention, are shown in FIG. 2. This cell operates quite differently from the prior art 1T1C cell. Instead of using the switched or non-switched charge as a signal (as in the 1T1C DRO cell) the magnitude of the drain current Id of the ferroelectric transistor is used to distinguish between the two logic states.
In the 1T-cell, shown in FIGS. 2a and 2b, if the polarization of the ferroelectric layer is down, the threshold voltage of the device is increased (to e.g., 1.5 volts) and the drain current is low (at a drain voltage Vd˜0.3 volt, less than the threshold voltage), representing, for example, a logic “0”. If the polarization is up, the threshold voltage of the device is decreased (to e.g., −2.5 volts) and the drain current is high, representing, for example, a logic “1”. To write a cell, the cell is selected and a positive or negative voltage is applied to the gate of the selected transistor to write either a logic “1” (polarization up) or a logic “0” (polarization down). To read a cell, the cell is selected and a small drain voltage is applied to the selected cell. The sense amplifier determines if the drain current is high or low, representing a logic “1” or “0”. See FIG. 2c. 
A read operation does not change the polarization state of the device and, therefore, does not destroy the information (“non destructive read-out” or NDRO). The device does, therefore, not fatigue under a read operation (it only fatigues under a write operation), a major advantage over DRO memories. In addition to a fatigue-free read operation, a NDRO scheme is faster since no restore operation is needed, shortening the write cycle. NDRO also is potentially more reliable, especially in adverse environments (e.g., radiation) as encountered in military and space applications, as there is never an instance where the memory state is unidentified where an upsetting event (e.g., single event upset or SEU) could inadvertently alter the state of the memory.
The cell shown in FIG. 2a has a much smaller footprint than any known ferroelectric storage cell. It is potentially the smallest possible ferroelectric memory cell and is as dense as a Flash memory cell, the densest of any competing nonvolatile semiconductor memory technologies.
The challenges of building such a 1T ferroelectric memory cell is that the ferroelectric material has to be deposited directly on silicon instead of a metallic bottom electrode as in the prior art devices. This means that requirements for the ferroelectric material are quite different. The switched polarization (Pr) should be in a range of 0.1 to 1 μC/cm2 and not as high as possible as in the prior art device. The dielectric permittivity should be as low as possible, ideally less than 20, and the leakage current over the operating voltage range (e.g. +−5 Volt) should be as low as possible. This applies both to electronic and ionic charge motion in the ferroelectric material, but most importantly for the slow moving ionic charge. In order for the information stored in a 1T cell to be preserved, the polarization charge cannot be compensated. Any ionic charge that would slowly drift through the films and accumulate at the ferroelectric interfaces to the electrodes could compensate the polarization charge over time and destroy the information.